1) Field of the Invention
This invention relates to semiconductor devices and more particularly to an improved method of producing electro static discharge (ESD) protection circuits.
2) Description of the Prior Art
A person taking an integrated circuit from its plastic wrapping material or walking across a room can generate up to 20,000 V. This effect is cause by triboelectricity--the electrical produced by rubbing two materials together. A triboelectric discharge in to a semiconductor integrated circuit can damage the circuit enough to cause either immediate or subsequent early life failure.
Although one can use proper preventative care during handling, an electro static discharge of hundreds of volts can occur. Circuit designers place protective networks on the input and output circuits on a chip to furnish an electrical path for discharge thereby preventing the generation of large voltages across the gate oxides of the input circuit devices.
FIG. 1 shows an ESD protection circuit 2 typically formed of a NMOS transistor having a wide channel width. FIG. 1 shows an input terminal 11, ESD circuit 2, resistor 5, V.sub.dd 15, V.sub.ss 9 and circuit input 13. Without a working ESD protection circuit 2, when a large voltage is discharged into the input terminal 11, it would pass through the product device transistor 4 and damage the gate oxide of the transistor 4. A working ESD circuit 2 would protect the transistor 4 from the high voltage discharge.
VLSI circuit manufactures are making devices with thinner gate oxide layers to increase the device speeds. Therefore, gate oxide thicknesses are being continuously reduced. The gate oxide in present circuits is approximately 100 .ANG. thick or less and will be thinner in future circuits. The dielectric breakdown strength of silicon dioxide (SiO.sub.2) is approximately 8 MV/cm. Therefore, a 100 .ANG. thick gate oxide will not sustain voltages more than about 8 Volts. In actual practice, gate oxides are thinner than 100 .ANG. and process variables make the gate oxides thinner in spots causing the actual sustainable voltage to be well below 8 V. This 8 V breakdown is less than junction breakdown voltages. These lower gate oxide breakdown voltages cause problems, especially in the gate oxides in the ESD protection circuit because ESD transient operating voltages are higher than the gate oxide breakdown voltage. When the gate oxide in the protection circuit breaks down, the ESD protection circuit does not function to protect the device circuit.
Therefore, as thinner gate oxides are used, the gate oxides in the ESD protection circuits are breaking down thus not allowing the ESD circuit to protect the input device circuits 13. The primary failure mechanisms of gate oxides in ESD protection circuit are thermal run-away at the drain junction and gate oxide breakdown. Recent studies have shown that gate oxide breakdown happens before the drain junction breakdown, especially using a thin gate oxide with a thickness less than 100 .ANG.. Using the conventional one step gate oxidation process, one uniform gate oxide layer is formed over the entire substrate so that the ESD circuit devices have the same gate oxide thicknesses as the input circuit product devices. Therefore, the solution of increasing the gate oxide thickness for the ESD circuit, while maintaining the current device circuit gate oxide thickness (.about.80 to 100 .ANG.), is not possible with the conventional one step gate oxidation process.
Therefore, there is a need to develop a process that will provide a higher gate oxide breakdown voltage (V.sub.g) on ESD circuit transistors while maintaining thin gate oxide thickness for product CMOS device circuits.